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Espressif Systems /ESP32-C2 /LEDC /TIMER1_CONF

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Interpret as TIMER1_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DUTY_RES 0CLK_DIV0 (PAUSE)PAUSE 0 (RST)RST 0 (TICK_SEL)TICK_SEL 0 (PARA_UP)PARA_UP

Description

Timer 1 configuration

Fields

DUTY_RES

This register is used to control the range of the counter in timer %s.
CLK_DIV

This register is used to configure the divisor for the divider in timer %s.

The least significant eight bits represent the fractional part.
PAUSE

This bit is used to suspend the counter in timer %s.
RST

This bit is used to reset timer %s. The counter will show 0 after reset.
TICK_SEL

This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.

1’h0: SLOW_CLK 1’h1: REF_TICK
PARA_UP

Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data